An electronic device having a display typically includes a graphics processing block with on-chip memory and processing resources dedicated to processing graphics data. This kind of architecture relieves the burden of graphics processing from the electronic device's main system memory and processing resources, thereby improving system performance.
Conventionally, however, efficient processing of graphics data requires the on-chip memory to be comparable in size to the resolution of the graphics display. Integrating an on-chip memory onto the graphics processing chip is therefore especially costly for devices that have moderate to high resolution graphics displays. Further, the size of the on-chip memory significantly affects the physical area occupied by the chip in the electronic device, imposing substantial challenges for mobile electronic devices where the available physical area is limited.
Yet even if the on-chip memory can be reduced in size, the available memory bandwidth (the rate at which data can be read from or stored into the on-chip memory) might nonetheless constrain the performance of the electronic device. That is, reducing the size of the on-chip memory may require an increase in memory transactions for processing a given amount of graphics data in a certain amount of time. Clock rates and/or data bus widths must be increased to support this increase in memory bandwidth, which in turn increases the power consumption of the electronic device. Again this imposes significant limitations on how much the on-chip memory can be reduced, especially in mobile electronic devices where power consumption is of great concern.